The present invention relates to an amplifier circuit operating at high speed, more particularly, to a discrete time amplifier circuit and an analog-digital converter incorporating the amplifier circuit.
Signal transmission and processing can be carried out easily and efficiently by converting analog signals into digital signals. For this reason, an analog-digital converter (hereafter abbreviated as an AD converter) is a device having important functions in wireless receivers for use in mobile telephones and the like.
As data transmission speed becomes higher owing to the broadbandization of the recent communication systems, the double sampling operation technology capable of alleviating the settling characteristics of an operational amplifier serving as an analog circuit becomes more important to simultaneously attain high data transmission speed and low current consumption.
Furthermore, in the case that an AD converter is incorporated in an IC of a compact apparatus, such as a mobile telephone, such an AD converter is an important element in reducing the size and current consumption of apparatuses. Moreover, a common-mode feedback circuit (hereafter abbreviated as a CMFB circuit) constituting an amplifier circuit inside an AD converter is also required to meet the needs for reducing the size and current consumption of apparatuses.
FIG. 19 is a circuit diagram of a conventional amplifier circuit described in Japanese Patent No. 3485895. This amplifier circuit is an offset compensation and nonlinear compensation type. As shown in FIG. 19, an input voltage Vin is input to a sampling capacitor C1 via a switch SW1. The sampling capacitor C1 is disposed between the switches SW1 and SW4 and connected to the input of a single-stage main amplifier 2 via the switch SW4. Furthermore, both terminals of the sampling capacitor C1 are connected to a reference voltage source 14 via switches SW2 and SW3.
A switched-capacitor circuit including a switched feedback capacitor C2 is connected between the input and the output of the main amplifier 2. One terminal of the switched feedback capacitor C2 is provided with a switch SW6 connected to the input of the main amplifier 2 and a switch SW7 connected to the reference voltage source 14. The other terminal of the switched feedback capacitor C2 is provided with a switch SW8 connected to the reference voltage source 14 and a switch SW9 connected to the output of the main amplifier 2. The output of the main amplifier 2 is connected to one terminal of a switched capacitor C3. The other terminal of the switched capacitor C3 is connected to the reference voltage source 14 via a switch SW11. A load circuit 4, for example, a delta-sigma modulator having a sampling capacitor C5, is connected to the output of the main amplifier 2.
The main amplifier 2 has source-connected MOS FETs 7 and 8, and the common sources of the MOS FETs 7 and 8 are connected to a constant current source 9. The drains of the FETs 7 and 8 are connected to a power source (voltage V+) via load devices (constant current load circuits) 5 and 6. The gate of the MOS FET 7 is connected to the input of the main amplifier 2, and the gate of the MOS FET 8 is connected to the reference voltage source 14. The main amplifier 2 is provided with a differential amplifier 10 to which signals from the constant current load circuits 5 and 6 are input, and the output of this differential amplifier 10 becomes the output Vout of the main amplifier 2.
An auxiliary amplifier 3 includes a pair of source-connected MOS FETs 11 and 12, and the sources thereof are connected to a constant current source 13. The gate of the MOS FET 12 is connected to the connection point between a switched capacitor C3 and a switch SW 11 via a switch SW10 and also connected to one terminal of a capacitor C4. The other terminal of the capacitor C4 is connected to the reference voltage source 14, the (+) input of the auxiliary amplifier 3 and the gate of the MOS FET 11. The drain of the MOS FET 12 is connected to the drain of the MOS FET 7 of the main amplifier 2. On the other hand, the drain of the MOS FET 11 is connected to the drain of the MOS FET 8 of the main amplifier 2.
In the conventional amplifier circuit configured as described above, the switches SW2, SW4, SW6, SW9, SW11, SW12 and SW14 simultaneously perform ON/OFF operations in response to a signal φ1. Alternately with the operations of these switches, the switches SW1, SW3, SW5, SW7, SW8, SW10, SW13 and SW15 simultaneously perform ON/OFF operations in response to a signal φ2. By the switching operations of the above-mentioned switches, the auxiliary amplifier 3 compensates for the input offset voltage of the main amplifier 2 in response to the offset error compensation voltage stored transiently in the capacitor C4.
However, since common-mode feedback control (CMFB control) cannot be performed at double sampling timing in the conventional amplifier circuit configured as described above, the output common-mode voltage varies every half cycle, and there is a problem in which the characteristics of the amplifier circuit deteriorate.
A fully differential amplifier circuit having a common-mode feedback circuit (CMFB circuit) is available as an amplifier circuit capable of performing CMFB control. FIG. 20 is a schematic block diagram showing a fully differential amplifier circuit having a CMFB circuit. As shown in FIG. 20, the CMFB circuit of the fully differential amplifier circuit is a circuit for performing feedback so that the output common-mode voltage Vcmo, i.e., the average value of two output voltages Vout+ and Vout−, becomes a predetermined value (reference voltage: Vref). This kind of CMFB circuit is broadly classified into two types: a continuous time CMFB circuit to/from which a continuous signal is input/output and a discrete time CMFB circuit for processing a cyclic or discrete signal.
The continuous time CMFB circuit feeds back the variation in the output common-mode voltage Vcmo from the reference voltage Vref to the fully differential amplifier circuit continuously. The continuous time CMFB circuit is formed of transistors and an operational amplifier and advantageous in that the output common-mode voltage can be fed back in response to double sampling timing.
However, the continuous time CMFB circuit is disadvantageous in that the circuit is complicated and that current consumption is increased since the circuit operates at all times. Furthermore, if the performance of the active elements used therein changes, the characteristics of the circuit change, and there is a problem in which the control range that can be used to ensure the credibility of the active elements used therein is restricted.
On the other hand, the discrete time CMFB circuit feeds back the variation in the output common-mode voltage Vcmo from the reference voltage Vref in one cycle period. The discrete time CMFB circuit is formed of capacitors and switches and has no operational amplifier. Hence, the circuit is simplified easily, and the characteristics of the circuit elements thereof do not vary significantly. For these reasons, the discrete time CMFB circuit is advantageous in that the control range that can be used is not restricted.
However, since the discrete time CMFB circuit performs sampling (single sampling) every cycle and cannot perform CMFB control at double sampling timing, there is a problem in which the output common-mode voltage varies every half cycle and the characteristics of the operational amplifier deteriorate. Moreover, since the discrete time CMFB circuit performs feedback every cycle, there is a problem in which the initial pull-in period elapsing until the steady state is attained takes time.
Since the conventional amplifier circuit shown in FIG. 19 cannot perform CMFB control at double sampling timing (circuit operation performed every half cycle) as described above, the output common-mode voltage varies every half cycle, and there is a problem in which the characteristics of the operational amplifier deteriorate.
Furthermore, the conventional continuous time CMFB circuit is disadvantageous in that the circuit is complicated and that current consumption is increased since the circuit operates at all times. Moreover, if the performance of the active elements used therein changes, the characteristics of the circuit change, and there is a problem in which the control range that can be used is restricted.
Still further, since the conventional discrete time CMFB circuit cannot perform CMFB control at double sampling timing, there is a problem in which the output common-mode voltage varies every half cycle and the characteristics of the operational amplifier deteriorate. Moreover, since the conventional discrete time CMFB circuit performs feedback every cycle, there is a problem in which the so-called settling time becomes long, that is, the initial pull-in period elapsing until the steady state is attained takes time.